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LHF16KTV
V CC =3.3V±0.3V, T A =-40°C to +85°C
Versions (5)
LH28F160S3H-L100
43
Sym.
t AVAV
t PHEL
t WLEL
t ELEH
t SHEH
t VPEH
t AVEH
t DVEH
Parameter
Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
WP# V IH Setup to CE# Going High
V PP Setup to CE# Going High
Address Setup to CE# Going High
Data Setup to CE# Going High
Notes
2
2
2
3
3
Min.
100
1
0
70
100
100
50
50
Max.
Unit
ns
μs
ns
ns
ns
ns
ns
ns
t EHDX
t EHAX
t EHWH
t EHEL
t EHRL
t EHGL
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to STS Going Low
Write Recovery before Read
5
5
0
25
0
100
ns
ns
ns
ns
ns
ns
t QVVL
t QVSL
t FVEH
t EHFV
V PP Hold from Valid SRD, STS High Z
WP# V IH Hold from Valid SRD, STS High Z
BYTE# Setup to CE# Going High
BYTE# Hold from CE# High
2,4
2,4
0
0
50
NOTE 6
ns
ns
ns
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A IN and D IN for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. V PP should be held at V PPH1/2/3 until determination of block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock-
bit configuration or STS configuration success (SR.7=1).
Rev. 2.0
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